SM chart for UART transmitter - Sync State function

Q.  In SM chart for UART transmitter, which state/s indicate/s the waiting of sequential machine for the rising edge of bit clock and the consequent clearing of low order bit of TSR in order to transmit logic '0' for one bit time?
- Published on 25 Nov 15

a. IDLE State
b. Sync State
c. Transmit_Data_State
d. All of the above

ANSWER: Sync State

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