1) Which function/s is/are provided by Integrated Memory Management Unit in 80386 architecture?
a. Optional on-chip paging
b. 4 levels of protection
c. Virtual Memory Support
d. All of the above
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2) Which unit in 80386 DX architecture plays a crucial role in the conversion of linear address to physical address?
a. Execution
b. Protection
c. Segmentation
d. Paging
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3) In Intel x86 architecture, which general purpose register is used for repeated string instructions as well as shift, rotate and loop instructions?
a. EAX (Accumulator)
b. ECX (Counter)
c. EDX (Data register)
d. EBP (Data Pointer)
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4) Which status flag in x86 family is used to enable or disable the interrupt especially when the Pentium processor operates in the virtual mode?
a. ID
b. VIP
c. VIF
d. AC
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5) Which control register in x86 family is reserved for future use and generally not adopted for current implementation?
a. CR0
b. CR1
c. CR2
d. CR4
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6) Which functional unit of ARM family architecture is responsible for upgrading the address register contents before the core reads or writes the next register value from memory location?
a. Data bus
b. Barrel Shifter
c. Incrementer
d. Instruction Decoder
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7) Which type of non-privileged processor mode is entered due to raising of high priority of an interrupt?
a. User mode
b. Fast Interrupt Mode (FIQ)
c. Interrupt Mode (IRQ)
d. Supervisor Mode (SVC)
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8) Abort mode generally enters when _______
a. an attempt access memory fails
b. low priority interrupt is raised
c. ARM processor is on rest
d. undefined instructions are to be handled
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9) In the process of pipelining, which instructions are fetched from the memory by the ARM processor during the execution of current instruction?
a. Previous
b. Present
c. Next
d. All of the above
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10) If the three stages of execution in pipelining are overlapped, how would be the speed of execution?
a. Higher
b. Moderate
c. Lower
d. Unpredictable
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11) Which parameter/s is/are included in 'Time to market' design metric of an embedded system?
a. Time to prototype
b. Time to refine
c. Time to produce in bulk
d. All of the above
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12) How is the nature of instruction size in CISC processors?
a. Fixed
b. Variable
c. Both a and b
d. None of the above
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13) What is/are the configuration status of control unit in RISC Processors?
a. Hardwired
b. Microprogrammed
c. Both a and b
d. None of the above
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14) At an active HIGH reset pin of 8051 microcontroller, for how many machine cycles should the positive going pulse be provided, if the power is switched ON?
a. only one
b. two
c. three
d. four
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15) While designing an embedded system, which sub-task oriented process allocates the time steps for various modules that share the similar resources?
a. Simulation and Validation
b. Iteration
c. Hardware-Software Partitioning
d. Scheduling
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16) In DAC 0808, which among the following is configured as a reference in addition to R-2R ladder and current switches?
a. Voltage amplifier
b. Current amplifier
c. Transconductance amplifier
d. Transresistance amplifier
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17) In DAC 0808, what is the high speed multiplying input slew rate?
a. 2 mA/μ sec
b. 4 mA/μ sec
c. 8 mA/μ sec
d. 16 mA/μ sec
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18) In LPC 2148, which among the following is/are the functions of Mask register?
a. Byte addressability
b. Relocation to ARM local bus for fastest posible I/O timing
c. Treating sets of port bits in the form of group without changing other bits
d. All of the above
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Answer
Explanation
Related Ques
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ANSWER: Treating sets of port bits in the form of group without changing other bits
Explanation:
No explanation is available for this question!
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19) What is the size range of the alphanumeric LCDs?
a. 1 to 8 characters
b. 8 to 80 characters
c. 100 to 150 characters
d. 250 to 400 characters
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20) In LCD, which pin/s is/are used to latch the data into the data register or command register?
a. RS pin
b. R/W
c. E
d. All of the above
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21) Which type of handshake packet indicates that the device is incapable of accepting data as it is supposed to be busy with some another task?
a. ACK
b. NAK
c. STALL
d. None of the above
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22) Which among the following is/are integrated by OTG controller in order to implement OTG dual-role device functionality?
a. Host Controller
b. Device Controller
c. Master-only I2C bus interface
d. All of the above
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23) In RS232 DB-9 connector standard, which signal is sent by DTE by alerting the DCE for the data communication purpose?
a. DTR
b. DSR
c. RTS
d. DCD
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24) In SPI bus, which signal line carries data from master to slave device & hence regarded as Slave Input/Slave Data In (SI/SDI)?
a. Master Out Slave In (MOSI)
b. Master In Slave Out (MISO)
c. Serial Clock (SCLK)
d. Slave Select (SS)
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25) Which mode of operation is exhibited by RS-485 standard?
a. Single ended
b. Differential
c. Both a and b
d. None of the above
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26) In Von Neumann architecture, which among the following handles all the operations of the system that are inside and outside the processor?
a. Input Unit
b. Output Unit
c. Control Unit
d. Memory Unit
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27) In CPU structure, where is one of the operand provided by an accumulator in order to store the result?
a. Control Unit
b. Arithmetic Logic Unit
c. Memory Unit
d. Output Unit
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28) In CPU structure, which register provides the address for fetching of data or instruction especially by means of processor?
a. Data Register
b. Instruction Register
c. Accumulator
d. Memory Address Register
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29) In CPU structure, what kind of instruction to be executed is held by an instruction Register (IR)?
a. Current (present)
b. Previous
c. Next
d. All of the above
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30) In ADSP 21xx architecture, which notation represents ALU overflow condition?
a. AC
b. AV
c. NE
d. EQ
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