Embedded Processors Test Questions Set - 2

1)   Which kind of low-order 16 bits control register is also regarded as 'Machine Status Word' (MSW) in order to make it compatible with i286?

a. CR0
b. CR1
c. CR2
d. CR3
Answer  Explanation  Related Ques

ANSWER: CR0

Explanation:
No explanation is available for this question!


2)   In the test registers, what do/does the linear address bit hold/s with respect to TLB (Translation Look-aside Buffers)?

a. Physical address
b. Selection between write and lookup of TLB
c. Tag field
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Tag field

Explanation:
No explanation is available for this question!


3)   For addressing in real mode, which segment plays a significant role in the storage of destination operands during the string operation?

a. Code Segment
b. Data Segment
c. Stack Segment
d. Extra Segment
Answer  Explanation  Related Ques

ANSWER: Extra Segment

Explanation:
No explanation is available for this question!


4)   In x86 architecture, which type of gate acts as an intermediary between code segments at different privilege levels (PLs)?

a. Call gates
b. Task gates
c. Interrupt gates
d. Trap gates
Answer  Explanation  Related Ques

ANSWER: Call gates

Explanation:
No explanation is available for this question!


5)   In Pentium processor, which write buffer is used by the pipeline ALUs in order to write the result to the memory?

a. External Snoop Write Buffer
b. Internal Snoop Write Buffer
c. Line Replacement Write Buffer
d. Write-back Buffer
Answer  Explanation  Related Ques

ANSWER: Write-back Buffer

Explanation:
No explanation is available for this question!


6)   Which stage associated with pipelining mechanism recognizes the instruction that is to be executed?

a. Fetch
b. Decode
c. Execute
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Decode

Explanation:
No explanation is available for this question!


7)   Which kind of addressing mode for memory access operands support pre-index and post-index in addition to the generation of memory address by an immediate value added to a register?

a. Register indirect addressing mode
b. Relative register indirect addressing mode
c. Base indexed indirect addressing mode
d. Base with scale register addressing mode
Answer  Explanation  Related Ques

ANSWER: Relative register indirect addressing mode

Explanation:
No explanation is available for this question!


8)   Which mnemonic implies 'plus' meaning in the branch instructions?

a. BPL
b. BEQ
c. BMI
d. BAL
Answer  Explanation  Related Ques

ANSWER: BPL

Explanation:
No explanation is available for this question!


9)   In the branch instructions of ARM, what does the mnemonic BVC imply?

a. Overflow Set
b. Carry Set
c. Carry Clear
d. Overflow Clear
Answer  Explanation  Related Ques

ANSWER: Overflow Clear

Explanation:
No explanation is available for this question!


10)   Which type of branching instructions of thumb possesses 11-bit address & is generally applicable for slightly longer jumps in order to implement the instructions like GOTO of high level languages?

a. Short Conditional Branch
b. Medium Range Unconditional Branch
c. Long Range Subroutine Calls
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Medium Range Unconditional Branch

Explanation:
No explanation is available for this question!


11)   Which types of an embedded systems involve the coding at a simple level in an embedded 'C', without any necessity of RTOS?

a. Small Scale Embedded Systems
b. Medium Scale Embedded Systems
c. Sophisticated Embedded Systems
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Small Scale Embedded Systems

Explanation:
No explanation is available for this question!


12)   Which microcontrollers are adopted for designing medium scale embedded systems?

a. 8-bit
b. 16-bit to 32-bit
c. 64-bit
d. All of the above
Answer  Explanation  Related Ques

ANSWER: 16-bit to 32-bit

Explanation:
No explanation is available for this question!


13)   In Cortex-A processor series, which among the following is the standalone and smallest processor in size constraints with high-end application support?

a. Cortex-A5
b. Cortex-A9
c. Cortex-A53
d. Cortex-A59
Answer  Explanation  Related Ques

ANSWER: Cortex-A5

Explanation:
No explanation is available for this question!


14)   Which interrupt controller is present in Cortex-A15 processor?

a. GIC-390
b. GIC-500
c. Integrated GIC
d. GIC-400
Answer  Explanation  Related Ques

ANSWER: Integrated GIC

Explanation:
No explanation is available for this question!


15)   In Cortex-R processor series, which among the following represent/s dual core configuration along with the space saving the floating point unit?

a. Cortex-R 4
b. Cortex-R 5
c. Cortex-R 7
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Cortex-R 5

Explanation:
No explanation is available for this question!


16)   For the supplied data, which edge level is necessary for LCD in order to latch the data?

a. High-to-Low
b. Low-to-High
c. High-to-High
d. Low-to-Low
Answer  Explanation  Related Ques

ANSWER: High-to-Low

Explanation:
No explanation is available for this question!


17)   In LCD, which function is executed by '0x05' hex command?

a. Shift display left
b. Shift display right
c. Clear display
d. Return cursor to home
Answer  Explanation  Related Ques

ANSWER: Shift display right

Explanation:
No explanation is available for this question!


18)   In LCD, which hex command performs the function of 'Display on, cursor on and blinking'?

a. 0x0A
b. 0x0C
c. 0x0E
d. 0x0F
Answer  Explanation  Related Ques

ANSWER: 0x0F

Explanation:
No explanation is available for this question!


19)   In DC motor interfacing, which field/s is/are generated by forcing current through the coil for spinning of the motor?

a. Electric field
b. Electrostatic field
c. Magnetic field
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Magnetic field

Explanation:
No explanation is available for this question!


20)   In DC motor interfacing, which modulation controls the duty cycle of square wave provided at the output by generating variation in the average DC voltage?

a. Amplitude Modulation
b. Frequency Modulation
c. Pulse Width Modulation
d. Phase Modulation
Answer  Explanation  Related Ques

ANSWER: Pulse Width Modulation

Explanation:
No explanation is available for this question!


21)   What is the value of maximum data rate in RS 232 standard?

a. 20 kb/s
b. 40 kb/s
c. 80 kb/s
d. 100 kb/s
Answer  Explanation  Related Ques

ANSWER: 20 kb/s

Explanation:
No explanation is available for this question!


22)   In Modbus Protocol, which codes are included in Request PDU?

a. Function code, Response data
b. Function code, Function data
c. Error code, Exception code
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Function code, Function data

Explanation:
No explanation is available for this question!


23)   Which category of function code represents the currently used codes by some companies especially for legacy products?

a. Public
b. User-defined
c. Reserved
d. Exceptions
Answer  Explanation  Related Ques

ANSWER: Reserved

Explanation:
No explanation is available for this question!


24)   In ISA, what is/are the application/s of Timer2 which acts as a speaker timer?

a. Date & time maintenance in RAM
b. General purpose timer
c. Diagnostic purpose
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Diagnostic purpose

Explanation:
No explanation is available for this question!


25)   In ISA, Timer 0 is also regarded as ______

a. System Timer
b. Refresh Timer
c. Speaker Timer
d. All of the above
Answer  Explanation  Related Ques

ANSWER: System Timer

Explanation:
No explanation is available for this question!


26)   Match the following STKY multiplier (MAC) flag notations with their meanings in ADSP 21 xx family architecture.

A. MOS ------------------ 1) Multiplier floating-point invalid operation
B. MIS ------------------- 2) Multiplier Underflow
C. MUS ------------------ 3) Multiplier floating-point overflow
D. MVS ------------------ 4) Multiplier fixed-point overflow


a. A-3, B-2, C-4, D-1
b. A-2, B-3, C-1, D-4
c. A-1, B-4, C-3, D-2
d. A-4, B-1, C-2, D-3
Answer  Explanation  Related Ques

ANSWER: A-4, B-1, C-2, D-3

Explanation:
No explanation is available for this question!


27)   In ADSP 21 xx architecture, how many previously executed instructions are stored in instruction cache of cache memory?

a. 4
b. 8
c. 16
d. 32
Answer  Explanation  Related Ques

ANSWER: 16

Explanation:
No explanation is available for this question!


28)   In TMS 320 C5X processor, which operation/s is/are performed by Compare Select & Store Unit (CSSU)?

a. Selection of large word in accumulator for storing into the data memory
b. Comparison between high & low word of accumulator
c. Maintain the record of transition histories
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


29)   In TMS 320 C5X processor, which memory segment provides interfacing to external memory mapped peripherals and also serves as extra data storage space?

a. Program Memory
b. Data memory
c. I/O Memory
d. All of the above
Answer  Explanation  Related Ques

ANSWER: I/O Memory

Explanation:
No explanation is available for this question!


30)   How are the instructions executed in DSP Processors?

a. In Parallel manner
b. In Sequential manner
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: In Parallel manner

Explanation:
No explanation is available for this question!