1) CMRR of a differential amplifier can be improved by decreasing ______.
a. Differential voltage gain
b. Common mode voltage gain
c. Both a and b
d. None of the above
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2) Which concept states that if one input terminal of an op-amp is at zero potential, then the other one also will be at zero potential?
a. Virtual short
b. Virtual ground
c. Zero input current
d. None of the above
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3) Which among the following is/are included in DC characteristics of op-amp?
a. Input bias current
b. Thermal drift
c. Both a and b
d. None of the above
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4) PSSR is an op-amp parameter which defines the degree of dependence on variations in _______.
a. temperature
b. pressure
c. power supply voltage
d. slew rate
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5) What is PSRR value of an ideal op-amp?
a. Zero
b. Unity
c. Infinite
d. Unpredictable
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6) Flicker noise is also regarded as _______.
a. Popcorn noise
b. 1/f noise
c. Both a and b
d. None of the above
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7) Popcorn noise is generated by abrupt variations in input bias current especially due to imperfect surface conditions of _______.
a. Conductor
b. Insulator
c. Semiconductor
d. None of the above
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8) Which among the following has a constant power spectral density over a wide frequency range?
a. White noise
b. Black noise
c. Pink noise
d. Blue noise
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9) Which among the following is/are responsible for electrical interactions?
a. Parasitic capacitance
b. Mutual inductance
c. Both a and b
d. None of the above
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10) The noise produced by the differential input stage can be reduced by the selection of __________.
a. Proper transistor type
b. Proper geometry
c. Adequate level of operating currents
d. All of the above
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11) In an inverting ideal integrator, which component exhibits the feedback path connection?
a. Resistor
b. Inductor
c. Capacitor
d. Diode
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12) In absence of any applied AC input signal, what would be the gain of an ideal integrator?
a. Zero
b. Unity
c. Infinity
d. Unpredictable
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13) As the frequency increases, input impedance of differentiator __________.
a. Increases
b. Decreases
c. Remains constant
d. None of the above
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14) In a buffer circuit, the voltage follower is placed _______ two networks in order to minimize the effect of loading on the first network.
a. Before
b. Between
c. After
d. None of the above
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15) Due to presence of a capacitor in feedback path, the output of an integrator varies ______
a. Gradually
b. Instantaneously
c. Intermittently
d. All of the above
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16) Which among the following circuits is also regarded/known as ' Threshold Detector '?
a. Window detector
b. Over voltage indicator
c. Level detector
d. Zero crossing detector
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17) In an inverting Schmitt Trigger circuit, the hysteresis ________ is also known as 'hysteresis width'.
a. voltage
b. current
c. resistance
d. power
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18) In hysteresis width, the hysteresis voltage is equal to _______ upper & lower threshold voltages (VUT & VLT).
a. sum of
b. difference between
c. product of
d. division of
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19) In a peak detector circuit, which component holds the peak value till a higher peak value is detected?
a. Diode
b. Inductor
c. Capacitor
d. MOSFET switch
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20) Among which of the following factors do/does the operation of sample and hold mode depend/s?
a. Input
b. Output
c. Position of switch
d. All of the above
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21) In DACs, gain error occurs due to _________.
a. offset voltages of op-amps
b. leakage current in the switches
c. error in feedback resistor value
d. error in current source resistance values
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22) Which among the following types of ADCs require/s the shortest conversion time?
a. Flash type
b. Successive Approximation
c. Dual Slope
d. All of the above
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23) In dual slope type of ADCs, an input hold time is _______.
a. Almost zero
b. Higher than that of flash type ADCs
c. Longest
d. All of the above
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24) In ADCs, it is possible to reduce the quantization error by _______the number of bits.
a. Increasing
b. Decreasing
c. Maintaining consistency in
d. All of the above
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25) In ADC 0809 acting as a CMOS device, how many analog inputs & channel multiplexers are present?
a. 2
b. 4
c. 8
d. 16
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26) Which characteristic of PLL is defined as the range of frequencies over which PLL can acquire lock with the input signal?
a. Free-running state
b. Pull-in time
c. Lock-in range
d. Capture range
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27) According to transfer characteristics of PLL, the phase error between VCO output & incoming signal must be maintained between _______ in order to maintain a lock.
a. 0 & π
b. 0 & π/2
c. 0 & 2π
d. π & 2π
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28) In VCO IC 566, the value of charging & discharging is dependent on the voltage applied at ______.
a. Triangular wave output
b. Square wave output
c. Modulating input
d. All of the above
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29) For a PLL IC 565 with timing resistor & timing capacitor of about 15 kΩ & 0.02μF respectively, what would be the value of output frequency (f0)?
a. 433.33 Hz
b. 833.33 Hz
c. 1000 Hz
d. 2500 Hz
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30) In AM detector using PLL, the phase detector is basically a multiplier which produces ________components of frequencies at its output.
a. Sum
b. Difference
c. Both a and b
d. None of the above
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31) In LM317 voltage regulator, the protective diodes do not allow the filter capacitors to discharge through ______current points.
a. High
b. Low
c. Both a and b
d. None of the above
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32) In LM317 voltage regulator, what is the minimum value of voltage required between its input & output in order to supply power to an internal circuit?
a. 1V
b. 3V
c. 5V
d. 10V
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33) Which type of IC voltage regulator exhibits continuous variation in the impedance of transistor in order to supply the desired load current?
a. Linear regulators
b. Switching regulators
c. Both a and b
d. None of the above
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34) Due to operation of series pass transistor in an active region of linear voltage regulator, ___________
a. The ripple contents in o/p voltage waveform is very low
b. Then there is no necessity of using high speed transitor
c. Both a and b
d. None of the above
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35) Which among the following are regarded as three-pin voltage regulator ICs?
a. Fixed voltage regulators
b. Adjustable voltage regulators
c. Both a and b
d. None of the above
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