1) Match the following :
1. Complementary Law ---------------------------- I) A + AB = A
2. AND Law --------------------------------------------- II) A + A = A
3. OR Law ------------------------------------ III) A.A = 0
4. Absorptive Law --------------------------------------- IV) (A′)′ = A
a. 1-I, 2-II, 3–III, 4-IV
b. 1-IV, 2-III, 3-II, 4–I
c. 1-III, 2-II, 3-I, 4-IV
d. 1-II, 2-III, 3-IV, 4-I
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2) According to property of Commutative law, the order of combining terms does not affect _____.
a. Initial result of combination
b. Final result of combination
c. Mid-term result of combination
d. None of the above
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3) Which property of MOS ICs make it applicable in LSI, VLSI and ULSI circuits?
a. High packing density
b. Low packing density
c. Moderate packing density
d. None of the above
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4) Which integration technique highlights the phase of CPU fabrication thereby producing the microprocessor for the very time?
a. LSI
b. MSI
c. VLSI
d. ULSI
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5) What are the possible maximum number of transistors integrated over the chip corresponding to the functioning capability of Ultra-Large Scale Integration (ULSI) technique?
a. 1 million
b. Less than 1 million
c. More than 1 million
d. Cannot predict
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6) Which are the fundamental inputs assigned or configured in the full adder circuit?
a. Addend, Augend & Sum
b. Augend, Sum & Input Carry
c. Addend, Augend & Input Carry
d. Addend, Sum & Input Carry
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7) Which gate must be interposed between the cascaded stages of a parallel binary adder comprising full adders for transmission purpose of carry C11 or C22 to the next stage?
a. OR gate
b. AND gate
c. EX-OR gate
d. NAND gate
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8) How does an arithmetic operation take place in binary adders?
a. By addition of two bits corresponding to 2n digit
b. By addition of resultant to carry from 2n-1 digit
c. Both a & b
d. None of the above
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9) What are the possible combinations of maxterms comprising 'n' variables with an accomplishment of an OR gate generation?
a. 2n-1
b. 2n+1
c. 2n
d. 2n+2
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10) The boolean functions which can be represented by the sum of minterms and product of maxterms can be categorized in _______.
a. Standard form
b. Canonical form
c. Both a & b
d. None of the above
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11) Which illustration from the below stated functions exhibits the conversion of product of maxterm form into sum of minterm form if the value of product of maxterm is F(x,y,z) = π (6,8,10,11)?
a. F (x,y,z ) = ∑ (7,9,12,13)
b. F (x,y,z) = π (7,9,12,13)
c. F (x,y,z) = σ ( 7,9,12,13)
d. F (x,y,z) = S (7,9,12,13)
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12) Which operation is denoted by the sum-of-product form of boolean expression consisting of AND terms?
a. ANDing
b. ORing
c. Both a & b
d. None of the above
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13) What are the OR terms present in product of sum form of the boolean expression called as?
a. minterms
b. maxterms
c. sum terms
d. product terms
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14) It is possible to change the non-standard form of boolean function to a standard form by using ______.
a. De-Morgan's Law / Theorem
b. Duality Law / Theorem
c. Complementary Law
d. Distributive Law
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15) Which combinational circuit is renowned for selecting a single input from multiple inputs & directing the binary information to output line?
a. Data Selector
b. Data Distributer
c. Both a & b
d. None of the above
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16) It is possible for an enable or strobe input to undergo an expansion of two or more mux ICs to the digital multiplexer with the proficiency of large number of _____.
a. Inputs
b. Outputs
c. selection lines
d. All of the above
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17) Which is the major functioning responsibility of the multiplexing combinational circuit?
a. Decoding the binary information
b. Generation of all minterms in an output function with OR-gate
c. Generation of selected path between multiple sources and a single destination
d. All of the above
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Answer
Explanation
Related Ques
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ANSWER: Generation of selected path between multiple sources and a single destination
Explanation:
No explanation is available for this question!
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18) Which method of combination circuit implementation is widely adopted with maximum output functions and minimum requirement of ICs?
a. Multiplexer Method
b. Decoder Method
c. Encoder Method
d. Parity Generator Method
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19) What is the normal operating condition of decoder corresponding to input & output states?
a. E=0 & Outputs at '0' logic state
b. E=1 & Outputs at '1' logic state
c. E=0 & Outputs at '1' logic state
d. E=1 & Outputs at '0' logic state
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20) Why are the enable lines specifically used for connecting two or more IC packages in accordance to its application in decoder circuit?
a. It allows the reduction of digital function into similar function with more inputs & outputs
b. It allows the expansion of digital function into similar function with more inputs & outputs
c. It allows the reduction of digital function into different function with more inputs & outputs
d. It allows the expansion of digital function into different function with more inputs & outputs
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Answer
Explanation
Related Ques
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ANSWER: It allows the expansion of digital function into similar function with more inputs & outputs
Explanation:
No explanation is available for this question!
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