Computer Architecture Organization questions and answers

Computer Architecture Organization questions and answers


(1) In a computer, whose average memory access time is 20ns has the page fault service time 10Ms. For every 106 memory accesses one page fault is generated. The effective access time for the memory is

(A) 10ns
(B) 43ns
(C) 30ns
(D) 25ns

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ANSWER: 30ns




(2) Let T1 be the time taken for a single instruction on a pipelined CPU and T2 be the time take for a single instruction on a non-pipelined but identical CPU. Comparing T1 and T2 we can say that

(A) T1=T2 + the time taken for one instruction fetch cycle
(B) T1(C) T1≤T2
(D) T1≥T2

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ANSWER: T1≥T2




For Questions 3 and 4 refer to the data given below:

A direct mapped cache whose size is 32Kbyte has a block size 32byte. 32-bit address is generated by the CPU.

(3) The number of bits needed for cache indexing is

(A) 10
(B) 15
(C) 5
(D) 20

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ANSWER: 10




(4) The number of tag bits needed is

(A) 17
(B) 20
(C) 22
(D) 25

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ANSWER: 17




(5) A and B are the data inputs and Y is the control input of a multiplexer. When Y = 0 data input A is selected and when Y = 1 data input B is selected. The connections required to realize the 2-variable Boolean function f = X+Z, without using any additional hardware are

(A) X to A, 0 to B, Z to Y
(B) Z to A, 1 to B, 0 to Y
(C) Z to A, 1 to B, X to Y
(D) X to A, 1 to B, Z to Y

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ANSWER: Z to A, 1 to B, X to Y




(6) If 1Mbyte is the board memory of a graphics card then the mode, which does not support card, is

(A) On a 14” monitor 1600x400 resolution with 16 million colors
(B) On a 17” monitor 1600x400 resolution with 256 colors
(C) On a 17” monitor 800x400 resolution with 16 million colors
(D) On a 14” monitor 800x800 resolution with 256 colors

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ANSWER: On a 14” monitor 1600x400 resolution with 16 million colors




(7) The following program is executed in an 8085 microprocessor.

MVI H, 5DH
MVI L, 6BH
MOV A, H
ADD L

The state of auxiliary carry (AC) and Carry flag (CY) are

(A) AC = 0 and CY = 0
(B) AC = 1 and CY = 1
(C) AC = 0 and CY = 1
(D) AC = 1 and CY = 0

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ANSWER: AC = 1 and CY = 0




(8) Match the following

i Indirect addressing p Loops
ii Immediate addressing q Pointers
iii Auto increment addressing r Constants

(A) i-p, ii-r, iii-q
(B) i-q, ii-p, iii-r
(C) i-r, ii-q, iii-p
(D) i-q, ii-r, iii-p

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ANSWER: i-q, ii-r, iii-p




(9) A CPU is connected with a device that is transferring data byte wise, at the rate of10Kbyte/s. Interrupt overhead = 4μs. The byte transfer time between the device interfaces register and CPU or memory is negligible. The minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode is

(A) 5
(B) 15
(C) 25
(D) 35

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ANSWER: 15




(10) A CPU that runs at a frequency of 1GHz has a five-stage pipeline. In the first stage of the pipeline, instructions are fetched. A conditional branch instruction computes the target address and evaluation of the condition is done in the third stage of the pipeline. Until the outcome of the conditional branch is known the process does not fetch the new instruction. In this program out of 109 instructions 20% are instruction of conditional branching. What will be the total execution time of the program is each instruction takes one cycle to complete on average?

(A) 1.0s
(B) 1.1s
(C) 1.2s
(D) 1.3s

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ANSWER: 1.2s




(11) The one that does not interrupt a running process is

(A) Scheduler process
(B) Power failure
(C) A device
(D) Timer

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ANSWER: Scheduler process




(12) 3 clock cycles are required for register to/from memory transfer. 1 clock cycle is required for Add with both operands in register and 2 clock cycles per word are required for instruction fetch and decode. What are the total number of clock cycles required to execute the program?

(A) 35
(B) 28
(C) 30
(D) 24

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ANSWER: 24




(13) A 4-way set associative cache, which is initially empty, has total 16 cache blocks. Total 256 blocks are present in the main memory. The request for the memory blocks is in the following order:

0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155

If LRU replacement policy is used the memory block that will not be in cache is

(A) 216
(B) 1
(C) 0
(D) 255

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ANSWER: 216




(14) To add 16-bit numbers, the number of full adders and half-adders required are

(A) 10 half-adders and 17 full-adders
(B) 1 half-adder and 15 full-adders
(C) 15 half-adder and 1 full-adders
(D) 17 half-adder and 0 full-adders

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ANSWER: 1 half-adder and 15 full-adders




(15) A four way set associative cache consists of 128 lines with a line size of 64 words. In the main memory the CPU generates a 20-bit address of a word. What are the number of bits in the TAG, LINE and WORD field respectively?

(A) 6, 5, 8
(B) 9, 4, 7
(C) 9, 5, 6
(D) 7, 5, 6

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ANSWER: 9, 5, 6




For Questions 16 and 17 refer to the data given below:

A machine has a byte addressable main memory of 216. Let us assume that in the system, direct mapped data cache that consists if 32 lines of 64byte each are used. In the main memory that

starts from the memory location of 1100H, a 50x50 two-dimensional array of bytes is stored. Data cache is initially empty and the complete array is accessed twice. Assume that in between the

two accesses the contents of data cache do not change.

(16) The total number of data cache misses that will occur is

(A) 41
(B) 53
(C) 46
(D) 56

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ANSWER: 56




(17) While accessing the array for the second time, lines of the data cache that will be replaced by new blocks are

(A) Line 0 to line 7
(B) Line 9 to line 15
(C) Line 4 to line 11
(D) Line 1 to line 9

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ANSWER: Line 4 to line 11




(18) Which one of the following statement is true for horizontal microprogramming?

(A) Compared to vertical microprogramming, it results in larger sized microinstructions.
(B) It uses one bit for each control signal
(C) Use of signal decodes is not required
(D) All of the above

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ANSWER: It uses one bit for each control signal




(19) To provide a memory capacity of 256Kbyte, the number of 32k x 1 RAM chips required are

(A) 64
(B) 32
(C) 128
(D) 8

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ANSWER: 64




(20) Consider a RAM chip that has the capacity of 1024 words of 8 bits each (1k x 8). How many 2 X 4 decoders with enable line are needed to construct a 16K X 16 RAM from 1K X 8 RAM?

(A) 4
(B) 8
(C) 7
(D) 5

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ANSWER: 5




(21) Consider an N-bit carry look ahead adder where N is a multiple of 4. This adder employs 4-bit ALU (ICS 74181) and 4-bit carry look ahead generator (74182). Using the best architecture for this adder the minimum time is

(A) Proportional to N
(B) A constant
(C) Proportional to log N
(D) Proportional to 1/N

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ANSWER: A constant




(22) In 8085 microprocessor, the TRAP interrupt mechanism

(A) Executes an instruction from memory location 20H
(B) Executes an instruction supplied by an external device through the INTA signal
(C) Executes a NOP
(D) None of the above

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ANSWER: Executes an instruction from memory location 20H




(23) 150, 120, 160 and 140 ns are the respective stage delays of a 4-state pipeline. 5ns is the delay of each register that is used between the stages. What is the total time taken to process 1000 data items on this pipeline assuming constant clocking rate?

(A) 150.1μs
(B) 165.5μs
(C) 170.3μs
(D) 400.5μs

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ANSWER: 165.5μs




(24) A disk pack has 16 surfaces and in each surface 128 tracks is present and on each track 256 sectors are present. In a sector 512 byte of data are stored in a bit serial manner. What are the capacity of the disk pack and the number of bits required to specify a particular section in the disk?

(A) 256 Gbyte, 20 bit
(B) 256 Gbyte, 64 bit
(C) 256 Mbyte, 8 bit
(D) 256 Mbyte, 19 bit

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ANSWER: 256 Mbyte, 19 bit




For Questions 25 and 26 refer to the data given below:

Consider a hard disk that has 63 sectors on each track, 10 platters each with 2 recording surfaces and 1000 cylinders. The address of each sector is given in the form of triple (c, h, s)

where c = cylinder number, h = surface number and s = sector number. The address of the 0th sector is (0,0,0), the address of the 1st sector is (0,0,1) and so on.

(25) What is the sector number if the address is (400, 16, 29)?

(A) 505037
(B) 505036
(C) 505050
(D) 505038

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ANSWER: 505037




(26) What is the address of 1038th sector?

(A) (0, 19, 10)
(B) (0, 16, 31)
(C) (0, 18, 30)
(D) (0, 21, 38)

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ANSWER: (0, 16, 31)




(27) The swap space in the disk is used for

(A) Saving process data
(B) Saving temporary HTML page
(C) Storing device drivers
(D) None of the above

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ANSWER: Saving process data




(28) The data TLB (Translation look aside buffer) in an instruction execution pipeline can be accessed earliest

(A) After data cache lookup has completed
(B) After effective address calculation has completed
(C) During effective address calculation
(D) Before effective address calculation has started.

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ANSWER: During effective address calculation




(29) Absolute addressing, Relative addressing, Based addressing and indirect addressing are the four addressing modes. The addressing modes that are suitable for program relocation at run time are

(A) Relative and Based addressing
(B) Absolute and Relative addressing
(C) Based and indirect addressing
(D) Absolute and indirect addressing

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ANSWER: Relative and Based addressing




(30) What will be the content of register A after the execution of following 8085 program?

MVI A, 55H
MVI C, 25H
ADD C
DAA

(A) 7AH
(B) 25H
(C) 55H
(D) 80H

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ANSWER: 80H




(31) Which one of the following statement is true for I/O redirection?

(A) Implies connection 2 programs through a pipe
(B) Implies changing name of a file
(C) Both A and B
(D) None of the above

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ANSWER: Implies connection 2 programs through a pipe




(32) For multiplying two n-bit numbers an array multiplier is used. What is the total delay of the multiplier if each gate in the circuit has a unit delay?

(A) θ (n)
(B) θ (log n)
(C) θ (1)
(D) θ (n²)

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ANSWER: θ (n)




(33) For RET instruction in 8085 microprocessor, the number of machine cycles required is

(A) 1
(B) 3
(C) 4
(D) 5

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ANSWER: 3




(34) For connecting a low memory to 8085 use

(A) HOLD
(B) INTR
(C) READY
(D) TRAP

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ANSWER: READY




(35) Which one of the following statement is true for the daisy chain scheme of connecting I/O devices?

(A) Separate interrupt pin is needed on the processor for each device.
(B) Useful for connecting slow device to the processor device
(C) Uniform priority to all devices
(D) Non-uniform priority to various devices

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ANSWER: Non-uniform priority to various devices




(36) From the following options the one that modifies the program counter, in 8085 microprocessor, is

(A) JMP and CALL instruction
(B) Only PCHL instruction
(C) Only ADD instruction
(D) All of the above

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ANSWER: Only ADD instruction




(37) The statement that is not true for a pipelined processor is

(A) All RAW hazards can be handled by Bypassing
(B) All register carried WAR hazards can be eliminated by register renaming
(C) By dynamic branch prediction, control hazard penalties can be eliminated
(D) All of the above

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ANSWER: All of the above




(38) What does an operating system do when an interrupt occurs?

(A) It always resumes execution of interrupted process after processing the interrupt
(B) It always changes state of interrupted process after processing the interrupt
(C) It ignores the interrupt
(D) None of the above

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ANSWER: It always resumes execution of interrupted process after processing the interrupt




(39) In 8085 microprocessor, RST 7.5 interrupt executes service routine from interrupt vector location

(A) 0078H
(B) 003CH
(C) 0038H
(D) 0001H

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ANSWER: 003CH




(40) _________________ is not a form of memory

(A) Translation look-a-side buffer
(B) Instruction register
(C) Instruction cache
(D) Instruction opcode

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ANSWER: Instruction opcode




For Questions 41 and 42 refer to the data given below:

Out of the two cache organizations, the first one is 32Kbyte 2-way set associative with 32Kbyte block size and the second one is of the same size but direct mapped. In both the organization

the size of the address is 32 bit. Latency of a 2-to-1 multiplexer is of 0.6ns and that of a k-bit comparator is k/10ns. Let X1 be the hit latency of the set associative organization and X2

be the hit latency of the direct mapped organization.

(41) What is the value of X1?

(A) 1.2ns
(B) 2.4ns
(C) 2.8ns
(D) 1.6ns

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ANSWER: 2.4ns




(42) What is the value of X2?

(A) 2.3ns
(B) 2.7ns
(C) 1.5ns
(D) 1.7ns

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ANSWER: 2.3ns




(43) Which one of the following statement is true for 2’s complement addition?

(A) When positive value is added to a negative value overflow cannot occur
(B) When there is a carry from sign bit addition overflow is flagged
(C) When the carries from sign bit and previous bit match overflow is flagged
(D) None of the above

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ANSWER: When positive value is added to a negative value overflow cannot occur




(44) MBR ← PC
MAR ← X
PC ← Y
Memory ← MBR

This is the sequence of micro operation. A possible operation performed by this sequence is

(A) Conditional branch
(B) Initiation of interrupt service
(C) Operand fetch
(D) Instruction fetch

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ANSWER: Initiation of interrupt service




(45) To implement a 4-bit multiplier the amount of ROM needed is

(A) 1 Kbits
(B) 4 Kbits
(C) 2 Kbits
(D) 64 bits

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ANSWER: 2 Kbits




(46) Why more than one words are put in one cache block?

(A) To exploit the spatial locality of reference in a program
(B) To exploit the temporal locality of reference in a program
(C) To reduce the miss penalty
(D) None of the above

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ANSWER: To exploit the temporal locality of reference in a program




(47) Which one of the following is true for RAID configuration of disks?

(A) It is used to provide Fault tolerance
(B) It is used to provide high data density
(C) Both A and B
(D) Neither A nor B

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ANSWER: Both A and B




(48) The statement that is true for the Return From Exception (RFE) instruction on the general purpose processor is

(A) An exception cannot be allowed to occur during execution of an REE instruction
(B) It must be a privileged instruction
(C) It must be a TRAP instruction
(D) All of the above

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ANSWER: All of the above




(49) The instruction when inserted at location X will ensure that the value of register A after program execution is the same as its initial value is

(A) ADD A, #1
(B) LRC A, #1
(C) RRC A, #1
(D) NOP

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ANSWER: RRC A, #1




(50) How is the 8085 microprocessor put in the wait state?

(A) Lower the READY input
(B) Lower the HOLD input
(C) Raise the READY input
(D) Raise the HOLD input

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ANSWER: Lower the READY input



Post your comment

    Discussion

  • for 46th question, answer is option A -Rahul Kumar (10/06/15)
  • for 46th question, answer is option A
  • Regardin ans correction --ques(22) In 8085 microprocessor, the TRAP interrupt mechanism -Rahul Kumar (10/06/15)
  • (22) In 8085 microprocessor, the TRAP interrupt mechanism

    (A) Executes an instruction from memory location 20H
    (B) Executes an instruction supplied by an external device through the INTA signal
    (C) Executes a NOP
    (D) None of the above

    View Answer / Hide Answer

    ANSWER: memory location 20H -->It should be 24H { not 20H}

    so answer is D- none of these

    Please do the change in answer,becoz it confuses others
  • RE: Computer Architecture Organization questions and answers -srinu (06/05/15)
  • Thank you sir
  • RE: Computer Architecture Organization questions and answers -Raja (02/20/15)
  • Very effective
  • RE: Computer Architecture Organization questions and answers -sri (06/11/14)
  • for 46th question, answer is option A

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