1) In logic synthesis, ________ is an EDIF that gives the description of logic cells & their interconnections.
a. Netlist
b. Checklist
c. Shitlist
d. Dualist
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2) Which level of system implementation includes the specific function oriented registers, counters & multiplexers?
a. Module level
b. Logical level
c. Physical level
d. All of the above
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3) Which among the following is/are taken into account for post-layout simulation?
a. Interconnect delays
b. Propagation delays
c. Logic cells
d. All of the above
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4) Which among the following operation/s is/are executed in physical design or layout synthesis stage?
a. Placement of logic functions in optimized circuit in target chip
b. Interconnection of components in the chip
c. Both a and b
d. None of the above
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5) In VHDL, which class of scalar data type represents the values necessary for a specific operation?
a. Integer types
b. Real types
c. Physical types
d. Enumerated types
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6) Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type?
a. Bit type
b. Bit_vector type
c. Boolean type
d. All of the above
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7) In composite data type of VHDL, the record type comprises the elements of _______data types.
a. Same
b. Different
c. Both a and b
d. None of the above
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8) Which among the following wait statement execution causes the enclosing process to suspend and then wait for an event to occur on the signals?
a. Wait until Clk = '1'
b. Wait on x,y,z
c. Wait on clock until answer > 80
d. Wait for 12 ns
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9) After an initialization phase, the simulator enters the ______phase.
a. Compilation
b. Elaboration
c. Execution
d. None of the above
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10) Which concept proves to be beneficial in acquiring concurrency and order independence?
a. Alpha delay
b. Beta delay
c. Gamma delay
d. Delta delay
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11) An event is nothing but ______ target signal, which is to be updated.
a. Fixed
b. Change on
c. Both a and b
d. None of the above
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12) Which functions are performed by static timing analysis in simulation?
a. Computation of delay for each timing path
b. Logic analysis in a static manner
c. Both a and b
d. None of the above
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13) Which among the following is/are regarded as the function/s of translation step in synthesis process?
a. Conversion of RTL description to boolean unoptimized description
b. Conversion of an unoptimized to optimized boolean description
c. Conversion of unoptimized boolean description to PLA format
d. All of the above
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Answer
Explanation
Related Ques
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ANSWER: Conversion of RTL description to boolean unoptimized description
Explanation:
No explanation is available for this question!
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14) In synthesis flow, which stage/s is/are responsible for converting an unoptimized boolean description to PLA format?
a. Translation
b. Optimization
c. Flattening
d. All of the above
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15) In synthesis flow, the flattening process generates a flat signal representation of _____levels.
A. AND
B. OR
C. NOT
D. EX-OR
a. A & B
b. C & D
c. A & C
d. B & D
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16) If the level of fan-out is beyond a limit in synthesis, it results in an insertion of buffer by ultimate effect of _____ the speed.
a. Enhancing
b. Reducing
c. Stabilizing
d. None of the above
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17) Which among the following constraint/s is/are involved in a state-machine description?
a. State variable & clock
b. State transitions & output specifications
c. Reset condition
d. All of the above
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18) Which among the following is/are identical in Mealy & Moore machines?
a. Combinational output signal
b. Clocked Process
c. Both a and b
d. None of the above
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19) Which method/s is/are adopted for acquiring spike-free outputs?
a. Moore machine with clocked outputs
b. Mealy machine with clocked outputs
c. Output-state machine
d. All of the above
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20) In SM chart for UART transmitter, which state/s indicate/s the waiting of sequential machine for the rising edge of bit clock and the consequent clearing of low order bit of TSR in order to transmit logic '0' for one bit time?
a. IDLE State
b. Sync State
c. Transmit_Data_State
d. All of the above
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21) The devices which are based on fusible link or antifuse are _________time/s programmable.
a. one
b. two
c. four
d. infinite
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22) Which among the following is/are not suitable for in-system programming?
a. EPROM
b. EEPROM
c. Flash
d. All of the above
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23) Simple Programmable Logic Devices (SPLDs) are also regarded as _____________.
a. Programmable Array Logic (PAL)
b. Generic Array Logic (GAL)
c. Programmable Logic Array (PLA)
d. All of the above
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24) In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and other interconnection discontinuities?
a. Power/Ground Noise
b. Crosstalk Noise
c. Reflection Noise
d. All of the above
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25) In floorplanning, placement and routing are __________ tools.
a. Front end
b. Back end
c. Both a and b
d. None of the above
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26) In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the interconnection density?
a. Placement
b. Global Routing
c. Detailed Routing
d. All of the above
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27) In CMOS inverter, the propagation delay of a gate is the/an _________ transition delay time for the signal during propagation from input to output especially when the signal changes its value.
a. Highest
b. Average
c. Lowest
d. None of the above
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28) In pull-up network, PMOS transistors of CMOS are connected in parallel with the provision of conducting path between output node & Vdd yielding _____ output.
a. 1
b. 0
c. Both a and b
d. None of the above
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29) For complex gate design in CMOS, OR function needs to be implemented by _______ connection/s of MOS.
a. Series
b. Parallel
c. Both series and parallel
d. None of the above
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30) In MOS devices, the current at any instant of time is ______of the voltage across their terminals.
a. constant & dependent
b. constant & independent
c. variable & dependent
d. variable & independent
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31) On the basis of an active load, which type of inverting CMOS amplifier represents low gain with highly predictable small and large signal characteristics?
a. Active PMOS load inverter
b. Current source load inverter
c. Push-pull inverter
d. None of the above
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32) An ideal op-amp has ________
a. Infinite input resistance
b. Infinite differential voltage gain
c. Zero output resistance
d. All of the above
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33) Stuck open (off) fault occur/s due to _________
a. An incomplete contact (open) of source to drain node
b. Large separation of drain or source diffusion from the gate
c. Both a and b
d. None of the above
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34) Which type/s of stuck at fault model exhibit/s the reduced complexity level of test generation?
a. Single
b. Multiple
c. Both a and b
d. None of the above
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35) Why is multiple stuck-at fault model preferred for DUT?
a. Because single stuck-at fault model is independent of design style & technology
b. Because single stuck-at tests cover major % of multiple stuck-at faults & unmodeled physical defects
c. Because complexity of test generation is reduced to greater extent in multiple stuck-at fault models
d. All of the above
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