Digital Electronics - GATE practice papers - Electronics & Communication
        
	  
	
	Here, you can read Digital Electronics multiple choice questions and answers with explanation.
        
											
	
		| 1)   What is the crucial function of Emitter-Coupled Logic (ECL) ? (Marks : 01) - Published on 19 Oct 15
 
 
 a. Least Power Consumption b. Saturated Logic Operation c. Highest Packing Density d. Maximum Power Consumption 
											                        
											                        | Answer 
											                                Explanation |  
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                                                                            ANSWER: Maximum Power Consumption
                                                                             Explanation: Transistors of ECL always operates in an active or cut-off regions &  never goes in saturation region thereby eliminating the storage time.
 ECL comprises difference amplifiers in addition to emitter followers. These emitter followers are utilized at the output of difference amplifiers for shifting the DC level by consuming maximum power at the requisite level.
 
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		| 2)   It the input clock frequency of eight flip-flops is 768kHz, then what would be the value of its output frequency? (Marks : 01) - Published on 19 Oct 15
 
 
 a. 2 kHz b. 3 kHz c. 6 kHz d. 18 kHz 
											                        
											                        | Answer 
											                                Explanation |  
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                                                                            ANSWER: 3 kHz
                                                                             Explanation: Given:
 Input frequency = 768 kHz
 The output frequency of eight flipflops = (1 / 28)  x  Input frequency
 = (1 / 28 ) x 768
 =  768 / 256
 =  3 kHz
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		| 3)   Which is the correct truth-table for J-K flip-flop? (Marks : 01) - Published on 19 Oct 15
 
 
 a.  b.  c.  d.  
											                        
											                        | Answer 
											                                Explanation |  
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                                                                            ANSWER: 
   Explanation: J-K Flipflop has an ability to overcome the drawbacks of S-R flipflops .
 When both the inputs of JK flipflop are zero, the output is Qn  while when both the inputs are 1, the output is the complement of Qn  i.e (Q
 n).
 When the inputs are in the form of '0' , '1' & '1','0' respectively, then the outputs are generated in accordance to the J input value; i.e, outputs are '0' & '1' respectively for both the conditions.
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