Parallel I/O Ports in 8051 - MCQs with AnswersQ1. Which signal from CPU has an ability to respond the clocking value of D- flipflop (bit latch) from the internal bus?
a. Write - to - Read Signal
b. Write - to - Latch Signal
c. Read - to - Write Signal
d. Read - to - Latch SignalView Answer / Hide Answer
Q2. Which among the below mentioned statements are precisely related to quasi-bidirectional port?
ANSWER: b. Write-to-Latch Signal
A. Fixed high pull-up resistors are internally connected
B. Configuration in the form of input pulls the port at higher position whereas they get pulled lower when configured as a source current
C. It is possible to drive the pin as output at any duration when FET gets turned OFF for an input function
D. Upper pull-up FET is always OFF with the provision of 'open-drain' output pin for normal operation of port
a. A, B, C, D
b. A, B & C
c. A & B
d. C & DView Answer / Hide Answer Q3. What happens when the pins of port 0 & port 2 are switched to internal ADDR and ADDR / DATA bus respectively while accessing an external memory?
a. Ports cannot be used as general-purpose Inputs / Outputs
b. Ports start sinking more current than sourcing
c. Ports cannot be further used as high impedance input
d. All of the aboveView Answer / Hide Answer
ANSWER: a. Ports cannot be used as general-purpose Inputs/Outputs