What are the major difficulties of pipeline conflicts in processors supporting pipe lining?

What are the major difficulties of pipeline conflicts in processors supporting pipe lining?



The following are the main reasons for pipe line conflicts in the processor:

- When the same resource is accessed at the same time by two different segments it results in resource conflicts. The only way to resolve this problem is to use separate data memories.

- In case an instruction's execution depends on the result of a previous instruction and that result is unavailable it leads to data dependency conflicts.

- Instructions that change the count of the PC can cause a lot of problems. This is prevalent particularly in the case of Branch instructions. A method to resolve this issue is known as delayed load where certain instruction are made to execute in a delayed manner to avoid conflicts.
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