Digital Electronics Test Questions Set 1

1)   Which among the bipolar logic families is specifically adopted for high speed applications?

a. Diode Transistor Logic (DTL)
b. Transistor Transistor Logic (TTL)
c. Emitter Coupled Logic (ECL)
d. Integrated Injection Logic (I2L)
Answer  Explanation  Related Ques

ANSWER: Emitter Coupled Logic (ECL)

Explanation:
No explanation is available for this question!


2)   Which type of unipolar logic family exhibits its usability for the applications requiring low power consumption?

a. PMOS
b. NMOS
c. CMOS
d. All of the above
Answer  Explanation  Related Ques

ANSWER: CMOS

Explanation:
No explanation is available for this question!


3)   Which type of output current flows towards or into the output terminal in a logic circuit?

a. Sourcing current
b. Sinking current
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Sinking current

Explanation:
No explanation is available for this question!


4)   Suppose that the digital IC family has a fan out of 6. It implies that the gate can supply the current to _______ of same family.

a. 6 inputs
b. 6 outputs
c. 12 nodes
d. 12 branches
Answer  Explanation  Related Ques

ANSWER: 6 inputs

Explanation:
No explanation is available for this question!


5)   Which kind of logical operation is performed by the gate shown below?

Logic Gate.png
a. Logical Multiplication
b. Inversion
c. Addition/ Subtraction
d. NOT EXOR
Answer  Explanation  Related Ques

ANSWER: Addition/ Subtraction

Explanation:
No explanation is available for this question!


6)   What does the below stated OR Law imply, while performing OR operation of an input with '1'?

Expression of OR Law: A+ 1 = 1


a. Output will always be equal to input
b. Output will always be high
c. Output will always be low
d. Output will always be same
Answer  Explanation  Related Ques

ANSWER: Output will always be high

Explanation:
No explanation is available for this question!


7)   Which De Morgan's theorem states that the complement of a sum is equal to the product of complements?

a. AB = A + B
b. A+B = A. B
c. A+B = A.B
d. AB = A + B
Answer  Explanation  Related Ques

ANSWER: A+B = A. B

Explanation:
No explanation is available for this question!


8)   How is the relation specified between input and output in logic circuits?

a. Switching equations
b. Truth-table
c. Logic diagram
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


9)   In the half subtractor combinational circuit, what does 'A' represent in the subtraction operation (A - B)?

a. Minuend bit
b. Maxend bit
c. Subtrahend bit
d. Suptrahend bit
Answer  Explanation  Related Ques

ANSWER: Minuend bit

Explanation:
No explanation is available for this question!


10)   Which is an incorrect rule of binary subtraction from the following?

a. 0 – 0 = 0
b. 0 – 1 = -1
c. 1 – 0 = 1
d. 0 – 1 = 1 with borrow '1'
Answer  Explanation  Related Ques

ANSWER: 0 – 1 = -1

Explanation:
No explanation is available for this question!


11)   What should be the output of converter, if a common anode display segment is to be turned 'ON'?

a. '0'
b. '1'
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: '0'

Explanation:
No explanation is available for this question!


12)   Which adder plays a crucial role in eliminating the problem associated with the inter-stage carry delay?

a. Half adder
b. full adder
c. BCD adder
d. Look-ahead carry adder
Answer  Explanation  Related Ques

ANSWER: Look-ahead carry adder

Explanation:
No explanation is available for this question!


13)   Which among the following is/are responsible for the occurrence of clock skew by introducing delays from different paths of clock generator to various circuits?

a. Different length of wires
b. Gates on the paths
c. Gating of clock to control the loading of registers
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


14)   Consider the cross-coupled inverter shown below. By performing reset and set operations, if the circuit continue to remain in reset and set states respectively,then what is the bit storage capacity of cross-coupled inverter?

Cross-coupled Inverter.png
a. 0
b. 1
c. 2
d. 4
Answer  Explanation  Related Ques

ANSWER: 1

Explanation:
No explanation is available for this question!


15)   Which is the prohibited state/ condition in S-R latch and needs to be avoided due to unpredictable nature of output?

a. S = R = 0
b. S = 0, R = 1
c. S = 1, R = 0
d. S = R = 1
Answer  Explanation  Related Ques

ANSWER: S = R = 1

Explanation:
No explanation is available for this question!


16)   What would be the characteristic equation of SR latch corresponding to the K-map schematic shown below?

K- Map of S-R Latch.png
a. S + RQn
b. S + RQn
c. S + RQn
d. S + RQn
Answer  Explanation  Related Ques

ANSWER: S + RQn

Explanation:
No explanation is available for this question!


17)   What does the data in parallel form of representation in registers, known as?

a. Temporal Code
b. Spectral Code
c. Special Code
d. Factorial Code
Answer  Explanation  Related Ques

ANSWER: Special Code

Explanation:
No explanation is available for this question!


18)   Which type of triggering is shown by the D flip flops in buffer registers for the temporary storage of digital words?

a. Positive level triggering
b. Negative level triggering
c. Positive edge triggering
d. Negative edge triggering
Answer  Explanation  Related Ques

ANSWER: Negative edge triggering

Explanation:
No explanation is available for this question!


19)   Referring to the diagram, if all inputs are loaded simultaneously and output is loaded bit by bit, then what will be the mode of operation for a shift register?

Shift Register.png
a. Serial Input Serial Output (SISO)
b. Serial Input Parallel Output (SIPO)
c. Parallel Input Serial Output (PISO)
d. Parallel Input Parallel Output ( PIPO)
Answer  Explanation  Related Ques

ANSWER: Parallel Input Serial Output (PISO)

Explanation:
No explanation is available for this question!


20)   When the mode control pin is connected to ground, Universal Shift Register acts as _______

a. Unidirectional register
b. Bidirectional register
c. Multi-directional register
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Bidirectional register

Explanation:
No explanation is available for this question!


21)   The output of Up counters goes on increasing due to _________

a. Transmission of clock pulses
b. Reception of clock pulses
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Reception of clock pulses

Explanation:
No explanation is available for this question!


22)   If the number of states in a counter are 2n, then the value of 'n' is ________

a. Less than the number of flip flops
b. Greater than the number of flip flops
c. Equal to the number of flip flops
d. Unpredictable
Answer  Explanation  Related Ques

ANSWER: Equal to the number of flip flops

Explanation:
No explanation is available for this question!


23)   Which sequential circuits are applicable for counting pulses?

a. Counters
b. Flip Flops
c. Registers
d. Latches
Answer  Explanation  Related Ques

ANSWER: Counters

Explanation:
No explanation is available for this question!


24)   Which type of triggering phenomenon is exhibited by Counters?

a. Edge
b. Level
c. Pulse
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Edge

Explanation:
No explanation is available for this question!


25)   Where do/does the status of memory element in a synchronous sequential circuit get/s affected due to change in input?

a. At an active edge of clock
b. At passive edge of clock
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: At an active edge of clock

Explanation:
No explanation is available for this question!


26)   Which type of memory elements are used in synchronous sequential circuits?

a. Clocked Flip flops
b. Unclocked Flip flops
c. Time Delay Elements
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Clocked Flip flops

Explanation:
No explanation is available for this question!


27)   According to Moore circuit, the output of synchronous sequential circuit depend/s on ______ of flip flop

a. Past state
b. Present state
c. Next state
d. External inputs
Answer  Explanation  Related Ques

ANSWER: Present state

Explanation:
No explanation is available for this question!


28)   From the generalized schematic of Moore circuit given below, what does the combinational circuit 'C1' known as?

Generalized Diagram of Moore Circuit.png
a. Previous state decoder
b. Present state decoder
c. Next state decoder
d. Output state decoder
Answer  Explanation  Related Ques

ANSWER: Next state decoder

Explanation:
No explanation is available for this question!


29)   Which among the following are used in programming array logic (PAL) for reducing the loading on inputs?

a. Input buffers
b. Output buffers
c. OR matrix
d. AND matrix
Answer  Explanation  Related Ques

ANSWER: Input buffers

Explanation:
No explanation is available for this question!


30)   If the number of nichrome fuse links in PAL are equal to 2M xn, then what does 'n' represent in it?

a. Number of inputs
b. Number of arrays
c. Number of outputs
d. Number of product terms
Answer  Explanation  Related Ques

ANSWER: Number of product terms

Explanation:
No explanation is available for this question!


31)   Which gates are used on the output side as buffers in order to provide a programmable output polarity in PAL 16 P8 devices?

a. AND
b. OR
c. EX-OR
d. NAND
Answer  Explanation  Related Ques

ANSWER: EX-OR

Explanation:
No explanation is available for this question!


32)   How many logic gates can be implemented in the circuit by complex programmable logic devices (CPLDs)?

a. 10
b. 100
c. 1000
d. 10000
Answer  Explanation  Related Ques

ANSWER: 10000

Explanation:
No explanation is available for this question!


33)   Which bus is used as input data bus by the control lines for a specific duration while performing write operation?

a. Uni-directional bus
b. Bi-directional bus
c. Multi- directional
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Bi-directional bus

Explanation:
No explanation is available for this question!


34)   Which operations are executed by the control line at logic '1' level?

a. Read
b. Write
c. Store
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Read

Explanation:
No explanation is available for this question!


35)   Which among the following is/are a/the major disadvantage/s of dynamic memory in shift registers?

a. Less power consumption
b. High packaging density
c. Necessity of additional circuitry for time to time refreshing
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Necessity of additional circuitry for time to time refreshing

Explanation:
No explanation is available for this question!


36)   Which among the following memories utilizes the electrical voltage for erasing purposes?

a. PROM
b. EAROM
c. RAM
d. CAM
Answer  Explanation  Related Ques

ANSWER: EAROM

Explanation:
No explanation is available for this question!


37)   The  ability of HDL to describe the performance specification of a circuit is regarded as ____

a. Test case
b. System case
c. Mark bench
d. Test bench
Answer  Explanation  Related Ques

ANSWER: Test bench

Explanation:
No explanation is available for this question!


38)   What does an entity specify in the VHDL program format?

a. List of all libraries associated with the design
b. Code properties of VHDL
c. Input/output pins of the circuit
d. The behaviour of circuit
Answer  Explanation  Related Ques

ANSWER: Input/output pins of the circuit

Explanation:
No explanation is available for this question!


39)   Which among the following is the correct way of declaring the standard library in VHDL?

a. std.standard_all
b. std_standard.all
c. standard_std_all
d. std.standard.all
Answer  Explanation  Related Ques

ANSWER: std.standard.all

Explanation:
No explanation is available for this question!


40)   Which mode in VHDL allows to make the signal assignments to a port of mode out by preventing it from reading?

a. In
b. Out
c. Inout
d. Buffer
Answer  Explanation  Related Ques

ANSWER: Inout

Explanation:
No explanation is available for this question!