1) Which among the below specified registors are addressable only from bank1 of RFS?
a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)
d. ADCON0 (07H)
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2) Which register acts as an input-output control as well as data direction register for PORTA in bank 2 of RFS?
a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)
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3) Which bank of RFS has a provision of addressing the status register?
a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2
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4) Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity for the external interrupt INT?
a. RBPU
b. INTEDG
c. PSA
d. RTS
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5) Where are the prescalar assignments applied with a usage of PSA bit?
a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer
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6) Where is the exact specified location of an interrupt flag associated with analog-to-digital converter?
a. INTCON
b. ADCON0
c. ADRES
d. PCLATH
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7) Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register?
a. GIE
b. ADIE
c. RBIE
d. TOIE
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8) When does it become possible for a bit to get accessed from bank '0' in the direct addressing mode of PICs?
a. Only when RPO bit is set 'zero'
b. Only when RPO bit is set '1'
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict
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9) Which bit/s should be necessarily cleared in OPTION (SFR) register in order to turn on the weak internal pull-ups of port B?
a. RPO
b. RPBU
c. RBIF
d. All of the above
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10) When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of 'interrupt on change'?
a. By configuring all the pins (RB4-RB7) as inputs
b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs
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Answer
Explanation
Related Ques
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ANSWER: By configuring all the pins (RB4-RB7) as inputs
Explanation:
No explanation is available for this question!
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11) Which digital operations are performed over the detected mismatch outputs with an intention to generate a single output RB port change output?
a. OR
b. AND
c. EX-OR
d. NAND
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12) What is the purpose of acquiring two different bits from INTCON register for performing any interrupt operation in PIC 16C61 / 71?
a. One for enabling & one for disabling the interrupt
b. One for enabling the interrupt & one for its occurrence detection
c. One for setting or clearing the RBIE bit
d. None of the above
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Answer
Explanation
Related Ques
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ANSWER: One for enabling the interrupt & one for its occurrence detection
Explanation:
No explanation is available for this question!
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13) Which among the below specified combination of interrupts belong to the category of the PIC 16C61 / 71?
a. External, Timer/Counter & serial Port Interrupts
b. Internal, External & Timer/Counter Interrupts
c. External, Timer 0 & Port B Interrupts
d. Internal, External, Timer 0 & PortA Interrupts
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14) Which condition results in setting the GIE bit of INTCON automatically?
a. Execution of retfie instruction at the beginning of ISR
b. Execution of retfie instruction at the end of ISR
c. Execution of retfie instruction along with interrupt enable bit
d. Execution of retfie instruction along with interrupt disable bit
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Answer
Explanation
Related Ques
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ANSWER: Execution of retfie instruction at the end of ISR
Explanation:
No explanation is available for this question!
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15) What kind of external edge-sensitive interrupt is generated due to transition effect at pin RBO/INT?
a. INT
b. RBO
c. INTF
d. All of the above
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16) Which bit-register pair plays a significant role in configuring the rising or falling edge triggering levels in external interrupts of PIC 16C61/71?
a. INTF bit - INTCON register
b. INTEDG bit - OPTION register
c. INT bit -INTCON register
d. INTE bit - OPTION register
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17) Consider the following statements. Which of them is /are incorrect?
a. By enabling INTE bit of an external interrupt can wake up the processor before entering into sleep mode.
b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
c. During the occurrence of interrupt, GIE bit is set in order to prevent any further interrupts.
d. goto instruction written in program memory cannot direct the program control to ISR.
a. A & B
b. C & D
c. Only A
d. Only C
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18) What is the purpose of setting TOIE bit in INTCON along with GIE bit?
a. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
b. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow interrupt
c. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
d. None of the above
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Answer
Explanation
Related Ques
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ANSWER: For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
Explanation:
No explanation is available for this question!
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19) Where do the conversion interrupt flag (ADIF) end after an accomplishment of analog-to-digital (ADC) conversion process?
a. INTCON
b. ADCON0
c. OPTION
d. None of the above
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20) How much time is required for conversion per channel if PIC 16C71 possesses four analog channels, each comprising of 8-bits?
a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs
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21) How much delay is required to synchronize the external clock at TOCKI in Timer '0' of PIC 16C61?
a. 2-cycles
b. 4-cycles
c. 6-cycles
d. 8-cycles
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22) Which command enables the PIC to enter into the power down mode during the operation of watchdog timer (WDT)?
a. SLEEP
b. RESET
c. STATUS
d. CLR
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23) Which bits play a crucial role in specifying the details or reasons associated with the system wake-up in WDT?
a. PD & TO
b. C & Z
c. DC & RPO
d. All of the above
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24) Which channel would be selected if the values of channel bits CHS0 & CHS1 are '1' & '0' respectively in ADC Status Register?
a. AIN0
b. AIN1
c. AIN2
d. AIN3
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25) Which bit is mandatory to get initiated or set for executing the process of analog to digital conversion in ADCON0?
a. ADIF
b. ADON
c. Go/!Done
d. ADSC1
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26) What would be the value of ADC clock source, if both the ADC clock bits are selected to be '1'?
a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC
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27) The functionalities associated with the pins RA0- RA3 in ADCON1 are manipulated by __________
a. PCFG1 & PCG0
b. VREF
c. ADON
d. All of the above
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28) Which among the below mentioned aspect issues are supported by capture/compare/PWM modules corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
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29) Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
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30) What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
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Answer
Explanation
Related Ques
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ANSWER: Generation of rectangular wave with programmable duty cycle with an user assigned frequency
Explanation:
No explanation is available for this question!
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31) What happens when the program control enters the Interrupt Service Subroutine (ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR
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Answer
Explanation
Related Ques
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ANSWER: CCP1F bit gets cleared in PIR1 by detecting new capture event
Explanation:
No explanation is available for this question!
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32) Which register is suitable for the corresponding count, if the measurement of pulse width is less than 65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
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33) The capture operation in counter mode is feasible when mode of CCP module is _________
a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization
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34) What is the fundamental role exhibited by the CCP module in compare mode in addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
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Answer
Explanation
Related Ques
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ANSWER: To vary the pin status in accordance to the precisely controlled time
Explanation:
No explanation is available for this question!
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35) How does the pin RC2/CCP1 get configured while initializing the CCP module in the compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
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