# Electronic Devices & Circuits - GATE practice papers - Electronics & Communication

Here, you can read Electronic Devices & Circuits multiple choice questions and answers with explanation.

1)   Consider the assertions S1,S2,S3 & S4

S1 : SiO2  acts as an isolation layer between the junctions in IC fabrication process
S2 : SiO2  acts as an isolation equipment/ material  between the  different devices
S3: SiO2   acts as a passivation layer by preventing undesired impurities over the silicon surface.
S4 : SiO2  acts  as a di-electric between poly-silicon gate and the channel of semiconductor

Which among them is/ are precise functions of silicon dioxide in an ion implantation  process?(Marks : 01)

- Published on 19 Oct 15

a. S1: Correct, S2: Correct, S3:Correct , S4: Correct
b. S1: Correct, S2: Incorrect, S3: Correct , S4 : Correct
c. S1: Correct, S2: Correct, S3 :Incorrect , S4 : Correct
d. S1: Correct, S2: Correct, S3 : Correct, S4 : Incorrect
 Answer  Explanation ANSWER: S1: Correct, S2: Correct, S3:Correct , S4: Correct Explanation: SiO2 performs the major functions associated with an ion implantation process in IC fabrication process. It serves to be a dielectric, isolation as well as passivation layer depending upon the type of application. It also allows the precise doping level of windows between SiO2 with greater proficiency at ion implantation process.

2)   Consider the below mentioned statements.

A1. Reduction in channel width & cross-sectional area
A2. Reduction in current density of channel

Which among them are the possible consequences in JFET upon the application of drain-to-source voltage (VDS)? (Marks : 02)

- Published on 19 Oct 15

a. Only A1 is true
b. Both A1 & A2 are true but A2 is not a reason for A1
c. Both A1 & A2 are true but A2 is a reason for A1
d. Both A1 & A2 are false
 Answer  Explanation ANSWER: Only A1 is true Explanation: JFET comprises a wedge-shaped channel & gate to source operates only under the revere biased condition. The reverse biasing of gate to source junction increases the input resistance of JFET. Hence, the channel width cross-sectional area get reduced upon the application of drain to source voltage. This ultimately increases the channel current density.

3)   Consider the below mentioned assertions :

A1 : Increase in doping level of p-type moves EF towards the centre
A2 : Increase in doping level of p-type moves EF away from the centre
A3: Increase in doping level of p-type results in downward shifting in EF
A4 : Increase in doping level of p-type results in an upward shifting in EF

Which among them is/are correct in accordance to the existence of fermi-level effect in P-type semiconductor?
(Marks : 02)

- Published on 19 Oct 15

a. A1 & A3
b. A2 & A4
c. A1 & A4
d. A2 & A3
 Answer  Explanation ANSWER: A1 & A3 Explanation: Fermi-Level in P-type semiconductor occurs exactly above the acceptor energy level. However, by increasing the addition of impurity during the existence of Fermi-level effect results in the downward shifting of p-type in fermi-level energy (EF) .Besides these, it also moves towards the centre with the rise in temperature level.

4)   Which phenomenon in BJT is responsible for reduction in the effective base-width due to reverse-biasing of base-collector junction? (Marks : 01)
- Published on 19 Oct 15

a. Hall Effect
b. Early Effect
c. Fermi-Level Effect
d. All of the above
 Answer  Explanation ANSWER: Early Effect Explanation: The effective base width decreases as compared to metallurgical base-width because the collector junction is in reverse-biased mode. This effect is also renowned as base -width modulation since effective base width exhibits variations in accordance to biasing conditions.

5)   The ratio of collector current to emitter current by maintaining collector to base voltage at a constant level  is usually  termed as ___________ (Marks : 01)
- Published on 19 Oct 15

a. Common Emitter Amplification Factor
b. Common Collector Amplification Factor
c. Common Base Amplification Factor
d. None of the above
 Answer  Explanation ANSWER: Common Base Amplification Factor Explanation: The point of operation that moves on the characteristic curve for AC operation is basically represented as, α AC = Δ Ic / Δ IE ( VCB = constant) where, α AC is expressed as common base short amplification factor. In DC mode of operation, collector current and emitter current are specified levels of current on the basis of majority carriers & hence can be relatively expressed as, α AC = Ic / IE

6)   Which process plays a crucial role in transforming the pattern or layout on the working mask of silicon wafer in an IC fabrication mechanism? (Marks : 01)
- Published on 19 Oct 15

a. Wafer Cleaning