VLSI Design & Technology Test Questions Set - 1

1)   The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.

a. Waveform Editor
b. Waveform Estimator
c. Waveform Simulator
d. Waveform Evaluator
Answer  Explanation  Related Ques

ANSWER: Waveform Editor

Explanation:
No explanation is available for this question!


2)   Which among the following is a process of transforming design entry information of the circuit into a set of logic equations?

a. Simulation
b. Optimization
c. Synthesis
d. Verification
Answer  Explanation  Related Ques

ANSWER: Synthesis

Explanation:
No explanation is available for this question!


3)   _________ is the fundamental architecture block or element of a target PLD.

a. System Partitioning
b. Pre-layout Simulation
c. Logic cell
d. Post-layout Simulation
Answer  Explanation  Related Ques

ANSWER: Logic cell

Explanation:
No explanation is available for this question!


4)   In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?

a. Floorplanning
b. Placement & Routing
c. Testing
d. Extraction
Answer  Explanation  Related Ques

ANSWER: Extraction

Explanation:
No explanation is available for this question!


5)   Among the VHDL features, which language statements are executed at the same time in parallel flow?

a. Concurrent
b. Sequential
c. Net-list
d. Test-bench
Answer  Explanation  Related Ques

ANSWER: Concurrent

Explanation:
No explanation is available for this question!


6)   In Net-list language, the net-list is generated _______synthesizing VHDL code.

a. Before
b. At the time of (during)
c. After
d. None of the above
Answer  Explanation  Related Ques

ANSWER: After

Explanation:
No explanation is available for this question!


7)   In VHDL, which object/s is/are used to connect entities together for the model formation?

a. Constant
b. Variable
c. Signal
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Signal

Explanation:
No explanation is available for this question!


8)   Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic nature?

a. Scalar
b. Access
c. Composite
d. File
Answer  Explanation  Related Ques

ANSWER: Access

Explanation:
No explanation is available for this question!


9)   Which type of simulation mode is used to check the timing performance of a design?

a. Behavioural
b. Switch-level
c. Transistor-level
d. Gate-level
Answer  Explanation  Related Ques

ANSWER: Gate-level

Explanation:
No explanation is available for this question!


10)   In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator?

a. Compilation
b. Elaboration
c. Initialization
d. Execution
Answer  Explanation  Related Ques

ANSWER: Elaboration

Explanation:
No explanation is available for this question!


11)   Which type of simulator/s neglect/s the intra-cycle state transitions by checking the status of target signals periodically irrespective of any events?

a. Event-driven Simulator
b. Cycle-based Simulator
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Cycle-based Simulator

Explanation:
No explanation is available for this question!


12)   Which among the following is not a characteristic of 'Event-driven Simulator'?

a. Identification of timing violations
b. Storage of state values & time information
c. Time delay calculation
d. No event scheduling
Answer  Explanation  Related Ques

ANSWER: No event scheduling

Explanation:
No explanation is available for this question!


13)   Which among the following is an output generated by synthesis process?

a. Attributes & Library
b. RTL VHDL description
c. Circuit constraints
d. Gate-level net list
Answer  Explanation  Related Ques

ANSWER: Gate-level net list

Explanation:
No explanation is available for this question!


14)   Register transfer level description specifies all of the registers in a design & ______ logic between them.

a. Sequential
b. Combinational
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Combinational

Explanation:
No explanation is available for this question!


15)   In synthesis process, the load attribute specify/ies the existing amount of _________load on a particular output signal.

a. Inductive
b. Resistive
c. Capacitive
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Capacitive

Explanation:
No explanation is available for this question!


16)   Which attribute in synthesis process specify/ies the resistance by controlling the quantity of current it can source?

a. Load attribute
b. Drive attribute
c. Arrival time attribute
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Drive attribute

Explanation:
No explanation is available for this question!


17)   Which type of digital systems exhibit the necessity for the existence of at least one feedback path from output to input?

a. Combinational System
b. Sequential system
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Sequential system

Explanation:
No explanation is available for this question!


18)   The output of sequential circuit is regarded as a function of time sequence of __________.
A. Inputs
B. Outputs
C. Internal States
D. External States


a. A & D
b. A & C
c. B & D
d. B & C
Answer  Explanation  Related Ques

ANSWER: A & C

Explanation:
No explanation is available for this question!


19)   The time required for an input data to settle _____ the triggering edge of clock is known as 'Setup Time'.

a. Before
b. During
c. After
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Before

Explanation:
No explanation is available for this question!


20)   Hold time is defined as the time required for the data to ________ after the triggering edge of clock.

a. Increase
b. Decrease
c. Remain stable
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Remain stable

Explanation:
No explanation is available for this question!


21)   An Antifuse programming technology is predominantly associated with _____.

a. SPLDs
b. FPGAs
c. CPLDs
d. All of the above
Answer  Explanation  Related Ques

ANSWER: FPGAs

Explanation:
No explanation is available for this question!


22)   In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage & current to device input.

a. Low
b. Moderate
c. High
d. All of the above
Answer  Explanation  Related Ques

ANSWER: High

Explanation:
No explanation is available for this question!


23)   Which programming technology/ies is/are predominantly associated with SPLDs and CPLDs?

a. EPROM
b. EEPROM
c. FLASH
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


24)   Before the commencement of design, the clocking strategy determine/s __________

a. Number of clock signals necessary for routing throughout the chip
b. Number of transistors used per storage requirement
c. Power dissipated by chip & the size of chip
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


25)   Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points?

a. H tree
b. Balanced tree clock network
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: H tree

Explanation:
No explanation is available for this question!


26)   Increase in the physical distance of H-tree _________the skew rate.

a. Increases
b. Stabilizes
c. Decreases
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Increases

Explanation:
No explanation is available for this question!


27)   Which type of MOSFET exhibits no current at zero gate voltage?

a. Depletion MOSFET
b. Enhancement MOSFET
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Enhancement MOSFET

Explanation:
No explanation is available for this question!


28)   In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials.

a. Increases
b. Remains constant
c. Decreases
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Increases

Explanation:
No explanation is available for this question!


29)   In DIBL, which among the following is/are regarded as the source/s of leakage?

a. Subthreshold conduction
b. Gate leakage
c. Junction leakage
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


30)   Which among the following can be regarded as an/the application/s of MOS switch in an IC design?

a. Multiplexing & Modulation
b. Transmission gate in digital circuits
c. Simulation of a resistor
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


31)   In MOS switch, clock feedthrough effect is also known as __________.

A. charge injection
B. charge feedthrough
C. charge carrier
D. charge ejaculation


a. A & B
b. B & C
c. C & D
d. B & D
Answer  Explanation  Related Ques

ANSWER: A & B

Explanation:
No explanation is available for this question!


32)   Which among the following is/are regarded as an/the active resistor/s?

a. MOS diode
b. MOS transistor
c. MOS switch
d. All of the above
Answer  Explanation  Related Ques

ANSWER: MOS diode

Explanation:
No explanation is available for this question!


33)   In testability, which terminology is used to represent or indicate the formal evidences of correctness?

a. Validation
b. Verification
c. Simulation
d. Integration
Answer  Explanation  Related Ques

ANSWER: Verification

Explanation:
No explanation is available for this question!


34)   Which among the following is regarded as an electrical fault?

a. Excessive steady-state currents
b. Delay faults
c. Bridging faults
d. Logical stuck-at-0 or stuck-at-1
Answer  Explanation  Related Ques

ANSWER: Excessive steady-state currents

Explanation:
No explanation is available for this question!


35)   Which among the following faults occur/s due to physical defects?

a. Process variations & abnormalities
b. Defects in silicon substrate
c. Photolithographic defects
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!